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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
FEATURES
* Three LVDS outputs on two banks, A Bank with one LVDS pair and B Bank with 2 LVDS output pairs * Using a 31.25MHz or 26.041666MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 560MHz to 700MHz * RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.63ps (typical) * 3.3V output supply mode * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS844003I is a 3 differential output LVDS Synthesizer designed to generate Ethernet referHiPerClockSTM ence clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I has 2 output banks, Bank A with 1 differential LVDS output pair and Bank B with 2 differential LVDS output pairs.
ICS
The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS844003I uses ICS' 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS844003I is packaged in a small 24-pin TSSOP package.
PIN ASSIGNMENT
DIV_SELB0 VCO_SEL MR VDDO_A QA0 nQA0 CLK_ENB CLK_ENA FB_DIV VDDA VDD DIV_SELA0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 DIV_SELB1 VDDO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT GND DIV_SELA1
BLOCK DIAGRAM
CLK_ENA Pullup DIV_SELA[1:0] VCO_SEL
Pullup
ICS844003I
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
QA0
00 /1 /2 (default) /4 /5 0 01 0 10 11
TEST_CLK Pulldown
nQA0
XTAL_IN
OSC
XTAL_OUT XTAL_SEL Pullup
1
Phase Detector
VCO
1
QB0
FB_DIV 0 = /20 (default) 1 = /24
00 01 10 11
/1 /2 /4 (default) /5
nQB0 QB1 nQB1
FB_DIV Pulldown DIV_SELB[1:0] MR
Pulldown
CLK_ENB Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 844003AGI www.icst.com/products/hiperclocks.html REV. A MAY 31, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Type Description Division select pin for Bank B. Default = Low. Pulldown LVCMOS/LVTTL interface levels. VCO select pin. When Low, the PLL is bypassed and the cr ystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the Pullup output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Output supply pin for Bank A outputs. Differential output pair. LVDS interface levels. Output enable Bank B. Active High outputs are enable. When logic HIGH, the output pairs on Bank B are enabled. When logic LOW, the output pairs are in a high impedance state. Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. Output enable Bank A. Active High output enable. When logic HIGH, the output pair in Bank A is enabled. When logic LOW, the output pair is in a high impedance state. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. Feedback divide select. When Low (default), the feedback divider is set for /20. When HIGH, the feedback divider is set for /24. LVCMOS/LVTTL interface levels. Analog supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 24 2 Name DIV_SELB0 DIV_SELB1 VCO_SEL
Input
Input
3
MR
Input
4 5, 6 7
VDDO_A QA0, nQA0 CLK_ENB
Power Ouput Input
Pullup
8
CLK_ENA
Input
Pullup
9 10 11 12 13 14 15, 16
FB_DIV VDDA VDD DIV_SELA0 DIV_SELA1 GND XTAL_OUT, XTAL_IN TEST_CLK
Input Power Power Input Power Input
Pulldown
17
Input
18 19, 20 21, 22
XTAL_SEL nQB1, QB1 nQB0, QB0
Input Output Output
Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Power supply ground. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the cr ystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to Pulldown pull to low state by default. Can leave floating if using the cr ystal interface. LVCMOS/LVTTL interface levels. Cr ystal select pin. Selects between the single-ended TEST_CLK or cr ystal interface. Has an internal pullup resistor so the cr ystal interface is selected Pullup by default. LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
Power Output supply pin for Bank B outputs. 23 VDDO_B NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP
844003AGI
Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor
Test Conditions
Minimum
Typical 4 51 51
Maximum
Units pF k k
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
QA0/nQA0 Output Frequency (MHz) 625 312.5 156.25 125 625 312.5 156.25 125
TABLE 3A. BANK A FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 DIV_SELA1 0 0 1 1 0 0 1 1 DIV_SELA0 0 1 0 1 0 1 0 1 FB_DIV 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank A Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 64.8
TABLE 3B. BANK B FREQUENCY TABLE
Inputs Crystal Frequency (MHz) 31.25 31.25 31.25 31.25 26.041666 26.041666 26.041666 26.041666 DIV_SELB1 0 0 1 1 0 0 1 1 DIV_SELB0 0 1 0 1 0 1 0 1 FB_DIV 0 0 0 0 1 1 1 1 Feedback Divider 20 20 20 20 24 24 24 24 Bank B Output Divider 1 2 4 5 1 2 4 5 M/N Multiplication Factor 20 10 5 4 24 12 6 4.8 QB0/nQB0 Output Frequency (MHz) 625 312.5 156.25 125 625 312.5 156.25 125
844003AGI
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Outputs QA /1 /2 /4 /5
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs DIV_SELA1 0 0 1 1 DIV_SELA0 0 1 0 1
Inputs DIV_SELB1 0 0 1 1 DIV_SELB0 0 1 0 1
Outputs QB /1 /2 /4 /5
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs FB_DIV 0 1 Feedback Divide /20 /24
Disabled
TEST_CLK
Enabled
CLK_ENx
nQA0, nQB0:nQB1 QA0, QB0:QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3E. CLK_ENA SELECT FUNCTION TABLE
Inputs CLK_ENA 0 1 QA0 LOW Active Outputs nQA0 HIGH Active
TABLE 3F. CLK_ENB SELECT FUNCTION TABLE
Inputs CLK_ENB 0 1 LOW Active Outputs QB0:QB1 nQB0:nQB1 HIGH Active
844003AGI
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REV. A MAY 31, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO_A, B IDD IDDA IDDO_A, B Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 99 10 52 Maximum 3.465 3.465 3.465 Units V V V mA mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V5%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB TEST_CLK, MR, FB_DIV DIV_SELA1, DIV_SELB0 DIV_SELB1, DIV_SELA0, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465V or 2.625V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = 3.465V or 2.625V, VIN = 0V -5 -150 Minimum 2 1.7 -0.3 -0.3 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 5 Units V V V V A A A A
IIH
Input High Current
IIL
Input Low Current
844003AGI
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 350 0 1.4 0 50 40 Maximum Units mV mV V mV
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency FB_DIV = /25 FB_DIV = /32 19.6 15.313 Test Conditions Minimum Typical Fundamental 27.2 21.25 50 7 1 MHz MHz pF mW Maximum Units
Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V5%, TA = -40C TO 85C
Symbol Parameter Test Conditions Output Divider = /1 fOUT Output Frequency Range Output Divider = /2 Output Divider = /4 Output Divider = /5 Minimum 560 28 0 140 112 3 Outputs @ Same Frequency Outputs @ Different Frequencies 625MHz (1.875MHz - 20MHz) 312.5MHz (1.875MHz - 20MHz) 156.25MHz (1.875MHz - 20MHz) 125MHz (1.875MHz - 20MHz) t R / tF Output Rise/Fall Time 20% to 80% 15 30 0.55 0.59 0.63 0.64 325 Typical Maximum 700 35 0 175 14 0 Units MHz MHz MHz MHz ps ps ps ps ps ps ps ps %
tsk(b) tsk(o)
Bank Skew, NOTE 1 Output Skew; NOTE 2, 4
tjit(O)
RMS Phase Jitter (Random); NOTE 3
odc Output Duty Cycle 50 NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
844003AGI
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
0 -10 -20 -30 -40 -50 -60
10Gb Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.63ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding 10Gb Ethernet Filter to raw data
100k 1M 10M 100M
OFFSET FREQUENCY (HZ)
844003AGI
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REV. A MAY 31, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
Phase Noise Plot
Noise Power
SCOPE
Qx
Power Supply +
Float GND
-
LVDS
nQx
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
RMS PHASE JITTER
nQA0, nQB0, nQB1 QA0, QB0, QB1
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
nQB0
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% 80% VSW I N G Clock Outputs 20% tR tF 20%
QB0 nQB1 QB1
tsk(b)
BANK SKEW
VDD
OUTPUT RISE/FALL TIME
VDD
out
out
DC Input
LVDS
100
VOD/ VOD out
DC Input
LVDS
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844003AGI
OFFSET VOLTAGE SETUP
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844003I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844003I has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
ICS844003I
Figure 3. CRYSTAL INPUt INTERFACE
844003AGI
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near
3.3V 3.3V LVDS + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS844003I is: 3394
844003AGI
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REV. A MAY 31, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
844003AGI
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REV. A MAY 31, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS844003I
FEMTOCLOCKSTMCRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Marking ICS844003AGI ICS844003AGI Package 24 Lead TSSOP 24 Lead Shipping Packaging tube 2500 tape & reel Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844003AGI ICS844003AGIT
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844003AGI
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